Silicon single crystal wafers, prepared by slicing a silicon single crystal ingot having been grown mainly with a Czochralski method (CZ method) and by polishing sliced wafers, are used as wafers for manufacturing semiconductor integrated circuits and other IC devices. In an IC device manufacturing process, various kinds of heat treatments are performed in diverse processes according to a configuration of the device.
When an excessive shear stress is applied to a wafer in such processes, a dislocation penetrating through the wafer is generated and this is observed as a slip. Warpage occurs in a wafer in which the slip is generated, and a slip dislocation becomes a cause of leak defect and significantly reduces device yield.
Since a thermal stress and a self-weight stress tend to increase, in particular, with a large-diameter wafer of 300 or more (mm), it is more likely that the slip is generated.
Meanwhile, when the silicon wafer is heat treated for 1 to 4 hours at a temperature of 1100 to 1300 (° C.) in a non-oxidizing atmosphere, wafer surface defects are effectively eliminated. However, the possibility of slip generation becomes high particularly in such a high temperature heat treatment.
It is considered that the slip may be generated when the shear stress based on a sum of the thermal stress and the self-weight stress generated in the wafer in the heat treatment process exceeds the shear strength of the crystal. Thus, many attempts have been made to design the process as shown in Non-Patent Document 1 such that the thermal stress may be equal or less than the shear strength of the crystal by obtaining the thermal stress and the self-weight stress generated in the heat treatment process in terms of calculation.
[Patent Document 1] Japanese Unexamined Patent Publication H09-190954;
[Patent Document 2] WO2003/003441;
[Patent Document 3] Japanese Unexamined Patent Publication 2003-68746;
[Patent Document 4] Japanese Unexamined Patent Publication 2003-249501;
[Patent Document 5] Japanese Unexamined Patent Publication 2006-040980;
[Patent Document 6] WO01/0034882;
[Patent Document 7] Japanese Unexamined Patent Publication 2003-243404;
[Patent Document 8] Japanese Unexamined Patent Publication 2005-203575;
[Patent Document 9] Japanese Unexamined Patent Publication H11-340239; and
[Patent Document 10] WO2005/071144.
[Non-Patent Document 1] Robert H. Nilson and Stewart K. Griffiths, Defects in Silicon III, Edited by T. Abe, W. M. Bullis, S. Kobayashi, W. Lin and P. Wagner (Electrochemical Society INC., Pennington N.J., 1999) Procceedings Volume 99-1, page 119;
[Non-Patent Document 2] M. Akatsuka, K. Sueoka, H. Katahama, and N. Adachi, Journal of The Electrochemical Society, Vol. 146 (1999) page 2683-2688;
[Non-Patent Document 3] Dimitris Mroudas and Robert A. Brown, Journal of Materials Research, Volume 6 (1991) page 2337; and
[Non-Patent Document 4] Toshiaki Ono, Wataru Sugimura, Takayuki Kihara, and Masataka Hourai, Silicon Materials Science and Technology X, Editors: H. Huff, H. Iwai, H. Richter, Electrochemical Society, Pennington, N.J., 2005, Volume 2 no. 2, p 109.
However, it is extremely difficult to avoid the slip generation in the high-temperature heat treatment with respect to the large-diameter silicon wafer. Also, it was believed that the wafer having a large amount of oxygen precipitates tended to have lower shear strength in accordance with the conventional view as shown in Non-Patent Document 1. This is because the crystal strength of the CZ silicon crystal is lowered by lowering the residual solid solution oxygen concentration inside the crystal due to progress of oxygen precipitation as the crystal strength is influenced by the oxygen concentration and the dislocation may be generated more readily by a strain that is brought by the oxygen precipitates.
However, it has been indicated that introduction of oxygen precipitates is effective for slip suppression as shown in Patent Documents 2, 3, 4, and 5 ever since it was pointed out by Patent Document 1 that a presence of oxygen precipitates has a slip suppressing effect.
Also, it is shown in Patent Documents 6, 7, and 8 that a slip suppressing effect acts on wafers in which an OSF (oxidation induced stacking fault) and a BSF (bulk stacking fault) are introduced. However, because the OSF is a defect caused by an oxygen precipitation nucleus and the BSF is a defect that is unavoidably accompanied by the oxygen precipitation, it is considered that the slip suppression effect is inherently the same effect as indicated in Patent Documents 1, 2, 3, 4, and 5.
Although it is indicated in Patent Documents 1, 2, 3, 4, and 5 that the introduction of oxygen precipitates causes a slip suppression effect, the strength may be lowered depending on the precipitation state as indicated in the conventionally accepted theory. However, it has not been disclosed whatsoever under what oxygen precipitation circumstances the strength against the slip is increased or decreased. This is because the relationship between the state of oxygen precipitates and the strength against the slip is completely unknown.
In general, the heat stress and the self-weight stress loaded on the wafer differ according to each heat treatment condition and the strength against the slip capable of suppressing the slip generation under such load may also differ accordingly. Therefore, the suitable oxygen precipitation state may also differ. Under such circumstances, it was the only way to determine the suitable condition by trial and error in the technologies disclosed in Patent Documents 1, 2, 3, 4, and 5. Therefore, it was necessary to fulfill an immense task of carrying out the whole heat processes, thereafter examining existence of the slip, and then selecting more suitable conditions by trial and error.